The guys at X-bit have posted a few details about Intel's upcoming Nehalem processors that will integrate a memory controller, & eventually, a graphics core.

"Already now Intel can reduce or increase cache sizes for various processors without many problems, whereas Advanced Micro Devices can enable or disable Hyper-Transport links within its processors depending on their positioning (e.g. AMD Opteron processors for multi-processor servers have three HT links, whereas Athlon 64 for 1P machines have only one HT link). But Intel wants to go even further and scale the number of memory controller channels."